From: Maxim Mikityanskiy <maximmi@nvidia.com>
Date: Tue, 6 Apr 2021 10:32:47 +0300
Subject: net/mlx5e: Remove lro_param from mlx5e_build_indir_tir_ctx_common()
Patch-mainline: v5.15-rc1
Git-commit: a402e3a7470d4c6b7792552e1a510ce72fda9f3e
References: jsc#SLE-19253

In order to reduce the list of parameters and to define clearer
responsibility for mlx5e_build_indir_tir_ctx_common(), stop passing
lro_param and instead call mlx5e_build_tir_ctx_lro() directly where
needed.

Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
 drivers/net/ethernet/mellanox/mlx5/core/en_main.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -3121,7 +3121,6 @@ static void mlx5e_cleanup_nic_tx(struct
 }
 
 static void mlx5e_build_indir_tir_ctx_common(struct mlx5_core_dev *mdev,
-					     struct mlx5e_lro_param *lro_param,
 					     bool inner_ft_support,
 					     u32 rqtn, u32 *tirc)
 {
@@ -3129,8 +3128,6 @@ static void mlx5e_build_indir_tir_ctx_co
 	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
 	MLX5_SET(tirc, tirc, indirect_table, rqtn);
 	MLX5_SET(tirc, tirc, tunneled_offload_en, inner_ft_support);
-
-	mlx5e_build_tir_ctx_lro(lro_param, tirc);
 }
 
 static void mlx5e_build_direct_tir_ctx(struct mlx5_core_dev *mdev,
@@ -3138,7 +3135,8 @@ static void mlx5e_build_direct_tir_ctx(s
 				       bool inner_ft_support,
 				       u32 rqtn, u32 *tirc)
 {
-	mlx5e_build_indir_tir_ctx_common(mdev, lro_param, inner_ft_support, rqtn, tirc);
+	mlx5e_build_indir_tir_ctx_common(mdev, inner_ft_support, rqtn, tirc);
+	mlx5e_build_tir_ctx_lro(lro_param, tirc);
 	MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
 }
 
@@ -3167,9 +3165,10 @@ int mlx5e_create_indirect_tirs(struct ml
 		memset(in, 0, inlen);
 		tir = &res->rss[tt].indir_tir;
 		tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
-		mlx5e_build_indir_tir_ctx_common(priv->mdev, &lro_param,
+		mlx5e_build_indir_tir_ctx_common(priv->mdev,
 						 priv->channels.params.tunneled_offload_en,
 						 indir_rqtn, tirc);
+		mlx5e_build_tir_ctx_lro(&lro_param, tirc);
 		mlx5e_build_indir_tir_ctx_hash(&priv->rx_res->rss_params,
 					       &tirc_default_config[tt], tirc, false);
 
@@ -3187,9 +3186,10 @@ int mlx5e_create_indirect_tirs(struct ml
 		memset(in, 0, inlen);
 		tir = &res->rss[i].inner_indir_tir;
 		tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
-		mlx5e_build_indir_tir_ctx_common(priv->mdev, &lro_param,
+		mlx5e_build_indir_tir_ctx_common(priv->mdev,
 						 priv->channels.params.tunneled_offload_en,
 						 indir_rqtn, tirc);
+		mlx5e_build_tir_ctx_lro(&lro_param, tirc);
 		mlx5e_build_indir_tir_ctx_hash(&priv->rx_res->rss_params,
 					       &tirc_default_config[i], tirc, true);
 		err = mlx5e_create_tir(priv->mdev, tir, in);