From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Fri, 7 Jul 2017 11:24:13 -0400
Subject: drm/amd/display: dal1.1 hwseq prog update
Git-commit: 4e5095ca06a00fda50e2fcc721b1f923478778a8
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -64,17 +64,13 @@ static void enable_dppclk(
plane_id,
dppclk_div);
- if (dppclk_div) {
- /* 1/2 DISPCLK*/
+ if (hws->shifts->DPPCLK_RATE_CONTROL)
REG_UPDATE_2(DPP_CONTROL[plane_id],
- DPPCLK_RATE_CONTROL, 1,
+ DPPCLK_RATE_CONTROL, dppclk_div,
DPP_CLOCK_ENABLE, 1);
- } else {
- /* DISPCLK */
- REG_UPDATE_2(DPP_CONTROL[plane_id],
- DPPCLK_RATE_CONTROL, 0,
+ else
+ REG_UPDATE(DPP_CONTROL[plane_id],
DPP_CLOCK_ENABLE, 1);
- }
}
static void enable_power_gating_plane(