From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 6 Mar 2018 22:35:19 -0500
Subject: drm/amdgpu/soc15: add support for vega12
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Git-commit: 692069a1a4f137bb45a3d43af576de8d1ff89c7d
Patch-mainline: v4.17-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Add the IP blocks, clock and powergating flags, and
common clockgating support.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -527,6 +527,7 @@ int soc15_set_ip_blocks(struct amdgpu_de
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_VEGA12:
amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
@@ -651,6 +652,11 @@ static int soc15_common_early_init(void
adev->pg_flags = 0;
adev->external_rev_id = 0x1;
break;
+ case CHIP_VEGA12:
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ adev->external_rev_id = 0x1; /* ??? */
+ break;
case CHIP_RAVEN:
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
@@ -883,6 +889,7 @@ static int soc15_common_set_clockgating_
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_VEGA12:
adev->nbio_funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
adev->nbio_funcs->update_medium_grain_light_sleep(adev,