From: Oscar Mateo <oscar.mateo@intel.com>
Date: Tue, 8 May 2018 14:29:29 -0700
Subject: drm/i915/icl: WaCL2SFHalfMaxAlloc
Git-commit: 6b967dc392090831954644549676409ca22fe8bf
Patch-mainline: v4.18-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- s/MACALLOC/MAXALLOC (Mika)
- C, not lisp (Chris)
References: HSDES#1405766107
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-8-git-send-email-oscar.mateo@intel.com
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
2 files changed, 11 insertions(+)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8269,6 +8269,10 @@ enum {
#define GEN11_HASH_CTRL_BIT0 (1 << 0)
#define GEN11_HASH_CTRL_BIT4 (1 << 12)
+#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
+#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
+#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(str
*/
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE);
+
+ /* Wa_1405766107:icl
+ * Formerly known as WaCL2SFHalfMaxAlloc
+ */
+ I915_WRITE(GEN11_LSN_UNSLCVC, I915_READ(GEN11_LSN_UNSLCVC) |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+ GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)