From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Fri, 29 Dec 2017 12:46:22 +0000
Subject: net: phy: marvell10g: update header comments
Patch-mainline: v4.16-rc1
Git-commit: 05ca1b327eed2b9abb48cbd013ca451032bd86b0
References: bsc#1119113 FATE#326472
Update header comments to indicate the newly found behaviour with XAUI
interfaces.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/phy/marvell10g.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -6,12 +6,18 @@
*
* There appears to be several different data paths through the PHY which
* are automatically managed by the PHY. The following has been determined
- * via observation and experimentation:
+ * via observation and experimentation for a setup using single-lane Serdes:
*
* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
*
+ * With XAUI, observation shows:
+ *
+ * XAUI PHYXS -- <appropriate PCS as above>
+ *
+ * and no switching of the host interface mode occurs.
+ *
* If both the fiber and copper ports are connected, the first to gain
* link takes priority and the other port is completely locked out.
*/